Hardware startup principle
Under normal conditions, PS-ON in POWER is high level. Only when PS-ON is at low level will POWER start working. As shown in the figure above, in normal conditions, SUSC# of SOUTHBRIDGE should be high level, because this signal is valid at low level. At this time, the pole base of the transistor is low level, the transistor is off, and 5V-SB is directly added to PS-ON, so that the power supply remains normal. POWER cannot send the PG signal to SOUTHBRIDGE, and the system cannot work. When POWER BUTTON BOARD triggers, SUSC# is low level. At this time, the base of the transistor is high level on, and 5V-SB is directly grounded, so PS-ON is Pull down, POWER works, and send PG signals to SOUTH BRIDGE, NOTTHBRIDGE and CPU. When SOUTH is connected to PG, CLOCK sent by CLOCK GENERATION starts working, and outputs RESET# to ISA, PCI, AGP bus, NORTH? BRIDGE receives PG, PCI, RESET# and CLOCK and outputs CORREST# to CPU. The CPU receives CORREST# signals, starts the operation and sends FFFFFF0 address through the south and north bridges point to BIOS. The hardware startup part ends here, and the system startup right is handed over to BIOS. Enter the soft startup state
Soft start process
The software startup process is mainly POST (Power On Self Test-Power On Self Test) of BIOS (Base Input Output System). After the CPU is working, the distribution of the system’s high-end memory is as follows.
…………………..
A0000…BFFFF: For VIDEO? MEMORY
C0000…C7FFF: for VGA BIOS
C8000…CFFFF: for I/O ROM
D0000…DFFFF is Optional ROM & Buffer Area
E0000…FFFFF: for the system BIOS
When the CPU is reset, CS=FFFF, IP=0000 is prepared to perform a POST self-test program from FFFF0, called FETCH. In each FETCH CODE cycle, 32 20-bit addresses will be sent continuously (data is obtained from the PCI total online in 8 times, and the data obtained by running one time is marked by the TRDY and IRDR signals on the PCI. During this period, SOUTH BRIDGE is responsible for transmitting each address to the ISA bus and from the BI. Data is obtained in the OS. Since there are only 8 bits of data on the BIOS and PCI BUS is 32 as the bus, SOUTH BRIDGE will send TRDY and IRDY signals to the CPU every time 4 times of reading BIOS data (marked by I/O TRDY#). After 8 times, the CPU starts executing the code in the data from FFFF0, and then performs the next FETCH. It is precisely in this way that the entire POST process of the BIOS is completed.